Timing problem eradication

When designing CPUs I always had a worry that the timing would be off and would cause some crazy errors like making the ALU do the same calculation but I have found the solution. When doing an ALU operation the registers should be updated on the falling edge, this is so the registers save the data then the ALU is shut off.
Below  is an example I built in Logisim, It's a simple counter circuit that tests my theory.

First design document

I have started the design document for CPloU, the following is a link to the first version.
Design document